The present invention relates to the distribution of clock signals generally and divided clock signals in particular.
Electronic devices, including programmable logic devices (“PLDs”) and other devices, often must interface with a variety of other devices. To the extent that the clock speed of a device's core and the data interfaces with which it must interact are substantially similar, the clock signal that runs the input/output (“IO”) circuits of the device can be at the same speed as the clock signal that runs the core circuits of the device. However, there is increasingly a need for PLDs to interact with data interfaces that have a higher clock speed than the maximum clock speed (“Fmax”) of the PLD core circuitry. To accomplish receiving off-chip data (and outputting data off-chip) at clock speeds higher than Fmax, it is necessary to run a portion of the periphery circuitry at one clock speed for interacting with the IO pins and run another portion of the periphery circuitry at a slower clock speed for interacting with the core. Therefore, there is a need to distribute two clock signals that have different frequencies to circuitry in the periphery.
Synchronization is a basic issue that clock signal distribution networks must address. Specifically, the challenge is to distribute a clock signal from a common source to dispersed areas of a chip while accounting for distribution delays so that the clock signal has substantially the same phase everywhere on the chip that it is distributed. Two known techniques for synchronous clock distribution include equal-branch-length clock trees and delay compensated clock networks. Equal-branch clock trees distribute the clock signal at branch endpoints that are substantially the same distance from the clock source, thus the propagation delay at the distribution points is substantially equal (and therefore the clock signal is substantially synchronized across the distribution points). Delay-compensated networks use delay chains to allow using different length distribution lines. Such networks have delay chains (including one or more delay elements) and compensate for the difference in route lengths by adding more delay elements on shorter length routes to even out the propagation delay at different distribution points.
However, both types of clock distribution networks are resource intensive. Delay-compensated networks have the additional disadvantage that the amount of delay imparted by individual delay elements can be affected by process, voltage and temperature (“PVT”) variations that make it even more difficult to achieve wide distribution of a synchronized clock signal. Therefore, if distribution of two different-speed clock signals is necessary, it is preferable to find a way of distributing a second clock signal in the periphery that does not require building an additional clock network using typical methods presently found in the art.